---
title: "Enabling AWS Cloud FPGA Development Using High-Level Vitis HLS"
source: "arXiv AI/CL/LG（论文）"
source_tier: "t2"
url: "https://arxiv.org/abs/2611.06829v1"
permalink: "https://feed.astralor.com/items/itm_21a3fbfd47df97a2ffc77e01"
published: "2026-11-04T17:44:04.000Z"
score: 57
channel: "tech"
tags: ["AI Agent","Enabling AWS Cloud","FPGA Development Using","High-Level Vitis HLS","AWS EC2","FPGA","Vitis HLS","HDK"]
---

# Enabling AWS Cloud FPGA Development Using High-Level Vitis HLS

## 速览

We present a toolchain for development of ML models on AWS EC2 F2 cloud FPGA infrastructure from high-level language, implementing a complete Vitis HLS to HDK bridge to AFI workflow that has been absent from the academi…

## 关键点

- We present a toolchain for development of ML models on AWS EC2 F2 cloud FPGA infrastructure from high-level language, implementing a complete Vitis HLS to HDK bridge to AFI workflow that has been absent from the academi…
- We introduce a four-level methodology (FP32 PyTorch, bit-accurate quantized Python, HLS C-simulation, physical FPGA) to aid in localizing errors, including FPGA-specific circuit errors.
- Together these tools allow coding agents to effectively implement FPGA designs from user directions, testing and debugging as needed.

## 全文

We present a toolchain for development of ML models on AWS EC2 F2 cloud FPGA infrastructure from high-level language, implementing a complete Vitis HLS to HDK bridge to AFI workflow that has been absent from the academic literature despite eight years of AWS FPGA availability. We introduce a four-level methodology (FP32 PyTorch, bit-accurate quantized Python, HLS C-simulation, physical FPGA) to aid in localizing errors, including FPGA-specific circuit errors. Together these tools allow coding agents to effectively implement FPGA designs from user directions, testing and debugging as needed. We document the deployment workflow, timing closure strategies, and practical HLS engineering decisions that proved crucial. We validate using TinyBERT fine-tuned for address Named Entity Recognition, implementing the embedding layer and the first of four encoder layers on the FPGA hardware. Our implementation streams weights from host DRAM, yielding poor performance compared to CPU/GPU implementations; we discuss forward paths.

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