---
title: "Hardware Design and Security in the Era of Chiplets and LLMs: A Unified Analysis"
source: "arXiv AI/CL/LG（论文）"
source_tier: "t2"
url: "https://arxiv.org/abs/2608.05063v1"
permalink: "https://feed.astralor.com/items/itm_c044b192288a18842136b2a5"
published: "2026-08-05T17:09:13.000Z"
score: 72
channel: "tech"
tags: ["EDA","Large Language Models","Chiplet","Hardware Security"]
---

# Hardware Design and Security in the Era of Chiplets and LLMs: A Unified Analysis

## AI commentary

> This paper places two of today's hottest hardware topics—chiplets and LLM-driven EDA—under one security framework, a rare and valuable perspective. For chip design teams, the most notable insight is the Root-of-Trust architecture based on 2.5D split manufacturing plus active interposers; for AI security researchers, the native threats in LLM-driven EDA pipelines also merit close attention.

## At a glance

This paper presents a unified analysis of security challenges arising from heterogeneous 2.5D chiplet systems and LLM-driven EDA flows. It covers attacks across architectural, logical, and physical levels—including hardware stacks for LLM acceleration—and reviews defenses such as 2.5D split manufacturing and active interposers for isolated Root of Trust, as well as protections for LLM-based EDA pipelines. It also discusses how LLM systems can advance hardware security for chiplet-era systems. The authors argue that these two revolutions compound security risks, requiring co-design of trust architecture and AI-assisted toolchains rather than isolated fixes.

## Key points

- Unified analysis of chiplet attack surfaces across architectural, logical, and physical levels, including hardware stacks for LLM acceleration.
- Proposes 2.5D split manufacturing and active interposers for physically isolated Root of Trust defenses.
- Identifies native threats and state-of-the-art defenses for LLM-driven EDA pipelines.
- Discusses how LLM systems can strengthen hardware security for modern systems such as chiplets.

## Full text

The semiconductor industry is undergoing a dual revolution: the shift toward heterogeneous 2.5D chiplet systems and the integration of Large Language Models (LLMs) into Electronic Design Automation (EDA) flows. While these paradigms offer unprecedented benefits in yield, modularity, design productivity, etc., they radically expand the hardware attack surface. This paper provides a unified analysis of these frontiers, ranging from attacks on chiplet systems (including hardware stacks for LLM acceleration) across architectural, logical, and physical levels, to various exploits against LLM-driven EDA pipelines. To secure chiplet systems, we review a powerful defense approach that leverages 2.5D split manufacturing and active interposers for physically isolated Root of Trust (RoT) architectures. To secure LLM-driven EDA pipelines, we first identify native threats and then review state-of-the-art defense techniques. Finally, we discuss how LLM systems can advance hardware security efforts for modern systems, including chiplets.

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