---
title: "小芯片与LLM时代下的硬件设计与安全：统一分析"
source: "arXiv AI/CL/LG（论文）"
source_tier: "t2"
url: "https://arxiv.org/abs/2608.05063v1"
permalink: "https://feed.astralor.com/items/itm_c044b192288a18842136b2a5"
published: "2026-08-05T17:09:13.000Z"
score: 72
channel: "tech"
tags: ["EDA","大语言模型","小芯片（Chiplet）","硬件安全"]
---

# 小芯片与LLM时代下的硬件设计与安全：统一分析

## AI 点评

> 这篇论文把两个当下最热的硬件话题——小芯片和LLM驱动的EDA——放在同一个安全框架里，视角很少见。对芯片设计团队来说，最值得关注的是2.5D拆分制造加有源中介层的信任根方案；对AI安全研究者而言，LLM驱动EDA管线的原生威胁也值得警惕。

## 速览

该论文提出首个统一框架，分析异构2.5D小芯片系统与LLM驱动EDA带来的安全威胁，涵盖架构、逻辑和物理层攻击，并梳理2.5D拆分制造与有源中介层实现物理隔离信任根、以及LLM驱动EDA管道防护等防御技术，最后探讨LLM系统如何助推小芯片安全。

## 关键点

- 统一分析小芯片系统在架构、逻辑、物理层面的攻击面，包括针对LLM加速硬件栈的攻击。
- 提出用2.5D拆分制造与有源中介层构建物理隔离信任根以防护小芯片系统。
- 分析LLM驱动EDA管道的原生威胁及现有防御技术。
- 讨论LLM系统如何反过来增强小芯片等现代系统的硬件安全。

## 全文

The semiconductor industry is undergoing a dual revolution: the shift toward heterogeneous 2.5D chiplet systems and the integration of Large Language Models (LLMs) into Electronic Design Automation (EDA) flows. While these paradigms offer unprecedented benefits in yield, modularity, design productivity, etc., they radically expand the hardware attack surface. This paper provides a unified analysis of these frontiers, ranging from attacks on chiplet systems (including hardware stacks for LLM acceleration) across architectural, logical, and physical levels, to various exploits against LLM-driven EDA pipelines. To secure chiplet systems, we review a powerful defense approach that leverages 2.5D split manufacturing and active interposers for physically isolated Root of Trust (RoT) architectures. To secure LLM-driven EDA pipelines, we first identify native threats and then review state-of-the-art defense techniques. Finally, we discuss how LLM systems can advance hardware security efforts for modern systems, including chiplets.

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